The present invention relates to a technique for transmitting a signal between semiconductor integrated circuit devices (ICs) and more specifically to a technique applied to and effective for an input/output circuit of a semiconductor integrated circuit device suitable for the transmission of a signal whose amplitude is small like GTL level (Gunning transceiver logic level). The present invention relates to, for example, a technique suitable for use in the transmission of a signal between semiconductor integrated circuit devices using buses functioning as signal transmission lines, which are employed in a data processing system wherein a plurality of babyboards or daughterboards are mounted on a so-called motherboard.
As a system for transmitting a signal between semiconductor integrated circuit devices, an interface system called "GTL (Gunning transceiver logic)" for performing transmission and reception of a signal whose amplitude is about 0.8 V (whose high level is 1.2 V and whose low level is 0.4 V) has been proposed (see Nikkei Electronics, Jun. 8, 1992, p.p. 133-141).
FIG. 8 is a circuit diagram showing a system for transmitting a signal between semiconductor integrated circuit devices under a GTL which has been discussed by the present inventors before the disclosure of the present invention. As shown in FIG. 8, an output circuit of a semiconductor integrated circuit device IC1 on the transmitting side is of an open-drain type or mode in which a drain terminal D of an output MOSFET (Metal-Oxide-Semiconductor Field Effect Transistor) Q1 is directly connected to an output pin (external output terminal) OUT. An input circuit IBF of a semiconductor integrated circuit device IC2 on the receiving side comprises a CMOS differential circuit (CMOS: Complementary-Metal-Oxide-Semiconductor Field Effect Transistor) electrically connected to an input pin (external input terminal) IN. A bus line (BUS line) used as a signal transmission line is provided between the output pin OUT and the input pin IN. Further, an terminal resistor Rt is connected between a node N1 supplied with a terminal voltage Vtt and the bus line.